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Catapult for a Power Optimized ESL Hardware Realization Flow

Catapult for a Power Optimized ESL Hardware Realization Flow

This paper describes, in general, the Catapult® flow for exploring low-power architectures, and it discusses in detail the low-power optimization results achieved using the Catapult Low-Power design flow. The case study was conducted using real customer designs. Designs were synthesized using Catapult with and without low-power optimizations turned on. With low-power optimizations on, Catapult uses Siemens EDA's PowerPro® technology under the hood for implementing RTL power optimization techniques and for estimating a design’s power usage.

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C/C++ to RTL Equivalence Checking for FPUs and More
Webinar

C/C++ to RTL Equivalence Checking for FPUs and More

This web seminar will highlight using Siemens' SLEC (Sequential Logic Equivalence Checking) technology to verify these complex circuits, including FMUL and FDIV.