Working smarter, not harder: NVIDIA closes design complexity gap with HLS
Success Story
By adopting a C++ High-Level Synthesis (HLS) flow using Catapult® from Siemens EDA, NVIDIA® was able to simplify their code by 5X, reduce the number of CPUs required for regression testing by 1000X, and run 1000X more tests to achieve higher functional coverage of their designs.
High-Level Synthesis (HLS) Decreased Design & Verification Time
HLS decreased design time by 50 percent and overall development time, including verification, by 40 percent, closing the gap between design complexity and the capacity to design. This paper will discuss the challenges NVIDIA faces in the ever-evolving world of video, camera, and display standards and the reasons an HLS/C-level flow makes it possible for them to succeed in this context.
関連情報
NVIDIA: High-Level Synthesis in Agile System-on-Chip Flows: Overview and Techniques
This talk provides a brief overview of NVIDIA Research’s use of Catapult HLS and highlights some useful features and flows of the Connections library, such as the ability to back-annotate SystemC simulations.
LG Electronics: Video Encoder IP Design Optimization and Verification Using Catapult
In this session, LGE describes a new design approach which concluded that adopting Catapult in IP development increases efficiency in time and cost, and they plan to increase usage in future IP projects.