Optimize your power methodology to more quickly achieve your PPW goals
In this white paper, we’ll review the many steps of today’s common ASIC/SoC power methodologies and tool flows. We’ll then propose ways you can further optimize your power methodology to more quickly achieve your PPW goals. Please note, while we acknowledge that energy consumption in digital CMOS logic is a combination of dynamic power and leakage, to keep this white paper to a digestible size we will primarily focus on optimizing a key factor of dynamic power consumption – specifically the switching power consumed by the charge and discharge of capacitances in various components like transistors, interconnect and at higher level memory blocks within an ASIC and SoCs. The key factor in the switching activity element of power consumption is stimulus. It is crucial to use realistic workloads during power estimation and analysis.