white paper

Machine Learning at the Edge: Using HLS to Optimize Power and Performance

Machine Learning at the Edge: Using HLS to Optimize Power and Performance

Moving machine learning to the edge has critical requirements on power and performance. Using off-the-shelf solutions is not practical. CPUs are too slow, GPUs/TPUs are expensive and consume too much power, and even generic machine learning accelerators can be overbuilt and are not optimal for power. In this paper, learn about creating new power/memory efficient hardware architectures to meet next-generation machine learning hardware demands at the edge.

Share

Related resources

Launching The Full Potential Of 3D IC With Front-End Architectural Planning
E-book

Launching The Full Potential Of 3D IC With Front-End Architectural Planning

Launching the full potential of 3D IC with front-end design planning

Semiconductor packaging: making the right connections in 3D IC design
E-book

Semiconductor packaging: making the right connections in 3D IC design

Regardless of substrate or interconnect technology, leading-edge companies can be confident in their 2.5D and 3D IC design flows when using Siemens.

Five key workflows for 3D IC packaging success
White Paper

Five key workflows for 3D IC packaging success

Learn about five workflow focus areas to adopt that provide immediate heterogeneous integration capability benefits needed for mainstream 2.5D and 3D IC chiplet design