The use of the PowerPro platform, outlined in this paper, provides ARM with an RTL design flow which is power-centric. The ability to perform daily RTL power analysis at the block/unit level provides rapid turnaround on the power trend, while weekly analysis provides more complete benchmark reference metrics.
Each element of the system can contribute to power consumption, but this paper focuses on designing power-efficient RTL IP, including:
Setting low-power objectives
Understanding the low-power design flow
Overall, the adoption of a unified RTL low-power methodology has helped Arm improve both RTL design efficiency and helped meet IP power goals by improving the PPA of their IP.