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white paper

Five key workflows for 3D IC packaging success

Abstract city-like visual depiction of chiplets connected in a 3D IC integrated package
As traditional monolithic solutions come within limits of manufacturing and physics, the semiconductor industry searches for viable alternatives. One trending solution is disaggregating SoC into solid, fabricated IP blocks known as chiplets. Engineers then interconnect multiple chiplets into a single 3D IC integrated package that delivers better performance at a reduced cost, higher yield, and a slightly larger area than standard SoC packages.

For successful implementation, semiconductor companies need standardized interface protocols that offer plug-and-play compatibility between chiplet suppliers. With new requirements and signoffs, how do workflows and design tools evolve to meet the new demands and resolve any challenges?

3D IC design workflow focus areas for heterogeneous integration

Five workflow adoption focus areas provide immediate heterogeneous integration capability benefits while establishing a managed methodology adoption and migration process that minimizes disruption, risk, and cost. These focus areas bring heterogeneous integration-based chiplet design within reach of mainstream manufacturers.

The five focus area workflows span several interlinked domain areas:

  • Architecture definition

  • Design activities (including planning, prototyping, system technology co-optimization, and detailed physical implementation of the substrates)

  • Multi-physics analysis

  • Device-level test

  • Manufacturing

Learn more about these 3D IC design workflows in the white paper.

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