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Dark matter, dark energy…What about dark errors?

Screenshot of a section of an IC design showing multiple DRC errors between polygons marked as waived.
The complexity of design rule checking (DRC) error waivers grows commensurate with the increase in design complexity and rules. Electronic design automation (EDA) tools continuously introduce new and enhanced automated waiver management capabilities to ensure design teams can capture and reference error waiver details from one design to the next. Are you getting full value from your waiver management process?

Automated DRC waiver management must constantly adapt to the growing complexity of IC designs to ensure accurate physical verification

Automated DRC waiver management functionality has been available for years, but the process has changed considerably as the number and complexity of rules increased at each node, along with the use of hard intellectual property (IP). Electronic design automation (EDA) software tools can now automatically capture a snapshot of the IP, its waivers, and the associated rules, and embed that data with the waivers and/or the IP to ensure waiver information is maintained as IP is used across multiple designs and process nodes. For “soft” IP, such as SRAM, waiver tools can capture and store typical patterns of legal SRAM configurations to enable designers to check their corresponding compiled SRAMs against these configurations. The same methodology can be used to safely waive known errors associated with these configurations.

The functionality used to quickly and safely identify DRC errors that do not require fixing is constantly expanding and improving to meet the new challenges presented with each new node and technology. Design companies should be sure they are using waiver technology that best supports their physical verification needs and processes.

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