Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis
Most hardware design teams have a verification methodology that requires a deep understanding of the RTL to reach their verification goals, but this type of methodology is difficult to apply to the machine generated RTL from High-level Synthesis (HLS). This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to close functional and structural coverage on HLS generated code.
Related resources
Semi-trunk routing
Semi-trunk routing capability allows the user to create a sketch plan that will only be routed on one end of the plan. This can help pre-route interfaces that may still require placement or pin and gate swapping optimization.
3D layout in PCB design
3D visualization during PCB design reduces iterations with the mechanical engineering team. Place components with first pass success, leading to less delays in completion of a high quality product.
Electronic design in product lifecycle
Xpedition EDM provides seamless integration between engineering and external PLM and ERP systems across the enterprise.