Technical Paper

Checking ESD path resistance in IC designs

To find and eliminate ESD issues, polygon segments with a resistance violation are highlighted in different colors based on the percentage contribution of each polygon to the total effective resistance of the ESD path.

Finding and eliminating ESD issues is critical to ensuring the reliability of IC chip designs, but it’s also difficult, requiring significant time and resources. The Calibre® PERC™ reliability platform provides a complete, automated checking solution for quickly and accurately detecting and debugging point-to-point resistance violations and bottlenecks in ESD paths, enabling designers to deliver even the largest and most complex IC designs on schedule without compromising performance reliability.

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