A better way to estimate breakdown voltage for ESD design windows
Accurately estimating upper breakdown voltage limits for ESD design windows ensures ESD protection devices adequately protect IC design circuitry against electrostatic discharge event
Meeting ESD design protection requirements is a critical part of today’s IC chip designs. The need to properly determine the upper voltage limit of an ESD design window exists in every scenario where an ESD protection device is used, but accurate estimates can be challenging. Using the breakdown voltage of the victim circuitry may be overly pessimistic, but overestimating the breakdown voltage may result in the victim circuitry being damaged before the ESD protection device fails or breaks down. The Calibre PERC reliability verification platform can automatically analyze a netlist and determine the lowest total breakdown voltage between any two given pins, enabling IC chip designers to more accurately estimate the best upper voltage limit for an ESD design window.