Catapult High-Level Synthesis and Verification Fact Sheet
Design Platform Empowering Designers
Catapult High-Level Synthesis (HLS) has been proven in production design flows with 1,000s of designs and the resulting RTL adheres to the strictest corporate design guidelines and ECO flows. In addition to Catapult HLS, only Catapult has integrated High-Level Verification tools and methodologies that enable designers to complete their verification signoff at the C++ level with fast closure for RTL. Discover this industry leading family of products.
Catapult HLS Productivity Gain
To achieve the maximum productivity gain from a C++/SystemC HLS methodology, it is necessary to have the performance and capacity to handle today’s large designs coupled with a comprehensive flow through verification and implementation.
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The Catapult High-Level Synthesis (HLS) library contains a set of modules to introduce Engineers to HLS and High-Level Verification.
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High-Level Synthesis (HLS) offers significant benefits when developing algorithms and intellectual property (IP).
Catapult for a Power Optimized ESL Hardware Realization Flow
This paper describes, in general, the Catapult® flow for exploring low-power architectures, and it discusses in detail the low-power optimization results achieved using the Catapult Low-Power design flow.
Closing Functional and Structural Coverage on RTL Generated by High-Level Synthesis
This paper describes innovative techniques to use with existing methodologies, for example the Universal Verification Methodology (UVM), to close functional and structural coverage on HLS generated code.