白皮书

High-Level Synthesis (HLS): status, trends and future directions

Picture showing a simple example of an algorithm that multiples four pairs of numbers and adds them. HLS tools create RTL based on choices the designer provides on how the function arguments map to hardware interfaces and other architectural constraints.

The transition to synthesis from higher levels of abstraction is taking place in the industry. Designing at abstraction levels higher than RTL offers significant advantages in verification, power/performance/area optimization, and design reuse. This paper provides perspectives on the ways in which High-Level Synthesis (HLS) is helping and shaping verification, power optimization, and design reuse. This transition is also changing the way hardware design is taught and the research projects that are enabled by the availability of mature HLS tools.

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