视频

仿真驱动型设计时代已经到来

设计团队每天都面临着难以实现的任务。在不知道设计性能的情况下如何创造新设计?观看此视频,进一步了解仿真驱动型设计如何帮助设计师更快提供产品。



单击视频可播放

分享

相关资源

Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
Webinar

Infineon: HLS Formal Verification Flow Using Siemens Formal Verification

High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc.

STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP
Webinar

STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP

STMicro presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) and a method to add constraints to the random values generated in UVMF.

CEA: Bridging the Gap Between Neural Network Exploration and Hardware Implementation
Webinar

CEA: Bridging the Gap Between Neural Network Exploration and Hardware Implementation

CEA presents a methodology that bridges the open-source DL framework N2D2 and Catapult HLS to help reducing the design process of hardware accelerators, making it possible to keep pace with new AI algorithms.

High-Level Synthesis & Advanced RTL Power Optimization – Are you still missing out?
Webinar

High-Level Synthesis & Advanced RTL Power Optimization – Are you still missing out?

Discover how C++ & SystemC/MatchLib HLS is more than just converting SystemC to RTL. In the RTL Design space, we will cover our technology for Power Optimization with PowerPro Designer & Optimizer.

Alibaba: Innovating Agile Hardware Development with Catapult HLS
Webinar

Alibaba: Innovating Agile Hardware Development with Catapult HLS

At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.

Space Codesign High-Level Synthesis for Hardware/Software Architectural Exploration of an Inferencing Algorithm
Webinar

Space Codesign High-Level Synthesis for Hardware/Software Architectural Exploration of an Inferencing Algorithm

Space Codesign Seminar: design flow including HW/SW co-design & HLS that allows developers to migrate compute intensive functions from software running on an embedded processor to a hardware based accelerator.