Harvard sheds light on their agile algo-hw co-design & co-verification
methodology powered by HLS. It led to an order of magnitude improvement in the
design effort across 3 generations edge AI accelerator SoCs.
Describes the design and verification of the systolic array-based DNN
accelerator taped out by Stanford, the performance optimizations of the
accelerator, and the integration of the accelerator into an SoC.
With constant change in AI/ML workloads, NVIDIA leverages a High-Level Synthesis
design methodology based off SystemC and libraries like MatchLib to maximizing
code reuse & minimizing design verification effort