技术论文

Shift left with Calibre to optimize IC design flow productivity, design quality, and time to market

Four circles connected by a continuous arrow wrapped around each circle, leading back from right to left. Circles contain icons representing “early detection,” “faster correction,” “increased productivity,” and “reduced cost.”

Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3D IC assembly before passing their work downstream for full signoff verification. However, waiting until signoff verification to find out how well you did is probably the least efficient approach to achieving production-ready layouts, impacting engineer productivity, project schedules, and hardware resources.

The shift left benefits in IC design verification

A shift left approach to IC design in which verification analysis is performed early and throughout the IC design cycle delivers significant competitive advantages. Early analysis capabilities available in the Calibre® nmPlatform toolsuite provide proven, innovative shift left solutions, including artificial intelligence, that allow design companies to achieve the productivity, efficiency, and cost reductions they are seeking while ensuring Calibre-quality results.

Download our technical paper to learn more.

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Calibre nmLVS-Recon 技术加快上市时间
Technical Paper

Calibre nmLVS-Recon 技术加快上市时间

Calibre nmLVS-Recon 工具使设计团队能够快速检查 “存在问题” 和不成熟的设计，以便更快、更早地发现并修复具有重大影响的电路错误，从而在总体上缩短流片排程和上市时间。