Managing system level netlist challenges for 3D IC assemblies in advanced package designs

The growing 3D IC technology for semiconductor products pushes the limits of single die designs, splitting a large die into multiple smaller dies. From a system-level design perspective, there are some challenges for the designer including ensuring that the assembly is physically connected as expected compared to design intent (captured as a system-level netlist). Capturing the system-level netlist is challenging in the case of multiple substrates because each substrate typically requires a different design team, methodology and/or format.

Read this whitepaper to learn more about the two key challenges electronic systems engineers face when deploying a system-level netlist driven LVS workflow for 3D IC assembly in advanced package designs.

To learn more read part 1 "System-level connectivity management and verification of 3D IC heterogeneous assemblies".

Netlist checking when deploying a system-level netlist-driven flow in 3D IC designs

One of the significant challenges when verifying the connectivity of a multi-substrate 3D IC design is the lack of one complete system source netlist. Since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, the designer must ensure that the netlist is golden.

Download this white paper to learn about a golden system-level netlist that reflects design intent and how to compare it to the physical assembly connection to ensure a correct build.

Connectivity planning and management exceptions for 3D IC designs

A system-level connectivity planning and management platform is essential to capture the interconnectivity of the different components in a 3D IC assembly. However, designers usually transition to this system-level EDA platform only after they have tested traditional approaches and experienced their shortcomings, mainly when the 3D IC system includes multiple substrates. Transitioning from conventional connectivity capture flows to advanced system-level flows.

Managing this challenge with 3D IC design flow connectivity exceptions, in which different design versions can include known opens and known shorts are waived for user-friendly, system-level LVS debugging and navigation.