Reducing verification risk with formal-based observation coverage

Ensuring an integrated circuit (IC) has been effectively tested during the verification process prior to fabrication remains a significant issue for electronics design teams. This is made worse by an inability to effectively measure verification progress. Various verification coverage techniques have been employed for this task, but they all exhibit certain drawbacks. This paper discusses the coverage issue and current solutions, including

methods for their improvement, before exploring the notion of observation coverage, a technique demonstrating significant promise as an effective verification closure metric.

The paper goes on to introduce Quantify™ observation coverage, a new, formal-based approach to coverage measurement that has been proven on real designs to increase verification confidence significantly. A discussion of this technique, its use on real designs, employed use models and verification flow integration are also included in the paper.

Verification cycle risk management

Logic design errors are a major concern in today’s system-on-chip (SoC) based approach to product development, due to the expensive delays and costly re-spins that result. Rigorous verification is, therefore, a necessity to ensure sufficient design quality prior to silicon fabrication and makes up a significant part of every SoC design flow.

Because of the ever-increasing complexity of SoC designs, logic verification remains a major challenge. As single tools and methodologies are unable to cope with all aspects of verification equally well, the modern verification process contains a variety of methodologies and tools that target specific aspects of verification. Examples include directed test-based simulation, constrained random simulation, emulation, prototyping and, of course, formal verification.

Having all these technologies in place raises other concerns, for example: How much verification do I need to perform, where do I need improved tests, and is my design ready for tape-out to the silicon fab?

The only way to control the verification process and minimize the risk of a remaining fault, or bug, to an acceptable level is to measure the quality of the verification performed so far. The common method of choice is verification coverage.