Design and verification using High-Level Synthesis (HLS) software

High-Level Synthesis (HLS) software has been in use in the industry for a number of years. Its adoption has been driven primarily due to the advantages that raising the level of abstraction of design has on reducing the ever-increasing costs of functional verification. The adoption of HLS has been driven by the need to tackle growing verification costs in traditional RTL design flows. This paper presents an overview of the design, optimization, and verification using HLS. It also outlines some of the requirements for HLS design to fit into existing design and verification flows and ways in which such flows might be adapted as HLS is more widely deployed.

Verification and low-power design

The high costs of verification in traditional manual RTL flows continues to be the main reason to move up design and verification to a higher level of abstraction. Verification is expected to be a major source of innovation as formal techniques and ways to complement it with simulation-based verification and a more rapid transition to emulation become mainstream. Some of techniques developed for RTL such as assertions and coverage will be applied to the C++ specification.

Another driver for HLS is low-power design. As HLS facilitates reuse of the C++ IP, it enables targeting an existing C++ to a new technology node to get hardware more highly optimized for power. As results show, HLS optimizations that understand the sequential properties of the design are able to better optimize the design and deliver additional power saving.