분석 보고서

The marine industry in 2030: Meet today’s challenges

Sustainable shipping will be at the heart of the marine industry in 2030. Increasing vessel performance will be key in shaping a green future.

Sustainable shipping is a major priority in marine today. The IMO has set ambitious emission targets for 2030 and 2050. Meeting them requires that vessel performance be optimized from design to operations.

Learn how digitalization can help you increase ship efficiency today and get ready for 2030!


About the “marine industry in 2030” thought-leadership series

What will the marine industry look like in 2030? We asked Monica Schnitger, naval architect and principal analyst at Schnitger Corporation, to answer this question for us. The result is a set of six briefs, each covering a different angle of the future of shipping. This brief focuses on one of the top challenges the marine industry is facing today: sustainable shipping.

More in the series

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관련 자료

CEA: Bridging the Gap Between Neural Network Exploration and Hardware Implementation
Webinar

CEA: Bridging the Gap Between Neural Network Exploration and Hardware Implementation

CEA presents a methodology that bridges the open-source DL framework N2D2 and Catapult HLS to help reducing the design process of hardware accelerators, making it possible to keep pace with new AI algorithms.

Infineon & Coseda: Facelifting a SystemC System Level Model Towards Physical Prototype – Adoption of High-Level-Synthesis
Webinar

Infineon & Coseda: Facelifting a SystemC System Level Model Towards Physical Prototype – Adoption of High-Level-Synthesis

Infineon & Coseda present on the adoption of High-Level-Synthesis at an existing SystemC system level model.

Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
Webinar

Infineon: HLS Formal Verification Flow Using Siemens Formal Verification

High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc.

STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP
Webinar

STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP

STMicro presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) and a method to add constraints to the random values generated in UVMF.

Alibaba: Innovating Agile Hardware Development with Catapult HLS
Webinar

Alibaba: Innovating Agile Hardware Development with Catapult HLS

At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.