Closing coverage in a High-Level Synthesis flow
While the speed up in verification time is a much-appreciated aspect of the HLS flow, teams strive to establish a methodology to easily close coverage at the C++ level and link those metrics to the RTL in the downstream flow. In the past, teams tried to use C++ software coverage tools to obtain coverage metrics. However, these tools do not understand hardware concepts causing misleading analysis and they have no links to the downstream RTL verification flow. That is why Siemens Digital Industries Software created Catapult Code Coverage (CCOV). CCOV brings the code coverage solution that RTL designers employ into the HLS world by using statement, branch, focused expression, and toggle coverage techniques to analyze C++ source code within the context of hardware. By writing the coverage results to the Questa Unified Coverage DataBase (UCDB), designers can use this data within the context of the proven Questa verification management tools. Check out this whitepaper to learn how to close coverage in an HLS flow.
Recursos relacionados
CEA: Bridging the Gap Between Neural Network Exploration and Hardware Implementation
CEA presents a methodology that bridges the open-source DL framework N2D2 and Catapult HLS to help reducing the design process of hardware accelerators, making it possible to keep pace with new AI algorithms.
Infineon & Coseda: Facelifting a SystemC System Level Model Towards Physical Prototype – Adoption of High-Level-Synthesis
Infineon & Coseda present on the adoption of High-Level-Synthesis at an existing SystemC system level model.
Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc.
STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP
STMicro presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) and a method to add constraints to the random values generated in UVMF.
Alibaba: Innovating Agile Hardware Development with Catapult HLS
At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.