Plug & Play DFT Solutions for HPC/AI

Modern high performance computing and artificial intelligence SoC designs have to deal with the integration challenges of huge amounts of IP cores - often from different sources. Joe Reynick, Technology Enablement Engineer at Siemens EDA, presents on behalf of Dongkwan Han of Samsung Foundry, about plug-and-play DFT solutions for HPC and and AI SoCs.

Tessent enables the Samsung design solution kit (DSK)

Samsung Foundries collaborated with Siemens to develop a new reference kit designed to help mutual customers substantially simplify and streamline DFT. In this video, originally presented at the 2021 International Test Conference, Siemens' Joe Reynick describes results from Dongkwan Han of Samsung Foundry on using Tessent plug & play DFT for 2.5D and 3D high-bandwidth memory (HBM) system-in-package designs.

Modern HPC/AI chips have massive amounts of core integration, lots of IP from different sources, and designers need to find the optimal test patterns for high-quality test that also speeds time-to-market. Test must be reliable and support large, hierarchical designs with many cores. Samsung now provides complete 2.5D and 3D solutions that support the development of chips for high-performance and artificial intelligence applications.

You will learn about:

• Samsung advanced test techniques, using Tessent SSN and hierarchical solutions
• High-quality test for HBM that supports more than just interconnect test
• Samsung flexible embedded core test solutions with IEEE 1687 (IJTAG)-compliant Tessent solutions