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System-level connectivity management and verification of 3D IC heterogeneous assemblies

Reading time: 10 minutes

Interposer floorplan view in a 3D IC heterogeneous assembly before importing the Verilog netlist

Integrating multiple dies and substrates into a single package continues to be a major focus of the semiconductors industry. Capturing the intended system-level connectivity in a multi-substrate 3D IC assembly can be a challenge. This is especially true when each substrate is built using a different methodology, team, and/or format.

Designers need an EDA platform such as Xpedition Substrate Integrator (xSI) that can aggregate the different formats for a multi-substrate system and generate a system-level netlist that drives assembly verification. Assembly verification using Xpedition Substrate Integrator and Calibre 3DStack is a “designer-centric” approach, as it is agnostic to the different die technology nodes and substrate manufacturers.

To learn more read part 2 "Managing system level netlist challenges for 3D IC assemblies in advanced package designs".