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SoC power methodology: Are we lean enough?

The Veloce Power App with Veloce PowerStream technology is completely scalable, and its runtime does not degrade with bigger design size.
It’s interesting how past lessons learned have such relevance in today’s quest for an optimum system-on chip (SoC) power methodology. Lean manufacturing was introduced by the Toyota® Motor Corporation in the 1930s. It is now an essential methodology in most manufacturing and industrial settings. As lean methodology evolved, it extended to software development where its principles have led to significantly better processes. Lean software development principles include eliminate waste, amplify learning, decide as late as possible, deliver as fast as possible, empower the team, build in quality, and see the whole.

In this paper, we look at how one of the lean concepts – eliminate waste – can be applied to the SoC power analysis flow. By approaching power with a “lean lens” we can look at ways to make the process more efficient while delivering the desired results.

A game changer: Veloce PowerStream technology

Veloce PowerStream™ is the latest innovation to the Veloce Power App. Veloce PowerStream allows power profiling at hundreds of KHZ (at real emulation speed). It also enables complete power profiling of realistic workloads and benchmarks deemed impossible before. For instance, a complete power profile of the Car Chase benchmark (Kishonti) was captured on Veloce using Veloce PowerStream technology in less than an hour while running on a big multi-core GPU. Typical power tools require a minimum of multiple weeks of processing to get a portion of this data and that’s based on the uncertain possibility of it happening at all. The Veloce Power App with Veloce PowerStream technology is completely scalable, and its runtime does not degrade with bigger design size.

With Veloce PowerStream, there is a significant reduction in waiting, overprocessing and data movement. In addition, the Veloce Power App monitors key power indicators (KPI) and metrics that significantly impact the power profile of a design, including:

• Static data from design related register, memory, clock-gating, etc.

• Register, clock, and combinational power

• Clock gating indicators (CGE, FFE)

• UPF power domain information

In addition, with Veloce PowerStream, power profiles and heat maps of a full SoCs can be generated within a couple hours while running real applications for billions of cycles. The design team can explore micro-architectural choices while running real applications and measure the impact on both power and performance and find the balanced trade off.

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