This paper describes the novel scan chain architecture that enables bi-directional shift operations during chain diagnosis and delves into the pattern generation needed to create a pattern set that allows diagnosis down to single cells. This new technology comprising scan chain design and diagnosis improves chain diagnosis resolution by 4X.
About reversible scan chain diagnosis
Scan chains help you test complex chip designs. But how do you test the scan chains themselves when they go wrong? Scan chain diagnosis has been leveraged to identify yield limiters in all phases of yield ramp.
For new technology nodes, test chips are used as characterization vehicles during the technology qualification stage. This stage is typically characterized by low yield and the volume of test chips is typically low. Scan chain failures could account for up to 66% of the chip failures (the rest being logic defects).
When silicon defects affect the scan chain path, chain diagnosis and EFI are employed to pinpoint the location of the defect and determine a root cause. Tessent can now leverage reversible scan chain architectures to generate patterns that improve scan chain diagnosis resolution.
The advantage of this method is that only chain test patterns are required for diagnosis. Since only failing chain test patterns are required, the diagnosis process also runs much faster. Enabling reversible chain diagnosis requires small changes to the design and the design flow.
This paper describes how reversible scan chain diagnosis works, how to generate patterns, presents design flows, and shows silicon results of reversible chain diagnosis.