Understanding die attach thermal performance for power electronics
Temperature fluctuations can result in the solder die attach breaking, the die attach delaminating from the die, or the die-attach separating from the substrate. Like a domino effect, this leads to higher temperature, which further damages the device, until complete failure.
Improves device performance and reliability
Extends the life of the product
Improve thermal performance with advanced testing solutions
Evaluating the effect of the voids on the thermal impedance of the die-attach, requires a highly sensitive measuring device and a method for determining the impact of the die attach on the overall measured thermal resistance
Thermal Structure Function analysis is a non-invasive way to visually find faults in the layers of a packaged device. Siemens Simcenter POWERTESTER tools measure current, voltage, and die temperature while utilizing structure function analysis to document package structure changes or defects.
Because it offers the requisite measurement accuracy, POWERTESTER 1500A was specifically utilized during testing. Coupled with the integrated structure function analysis of the Zth curve, it can determine the partial thermal impedance caused by die attach. Analysis of automatically captured data was done with Simcenter T3STER Master software.
Die attach solutions to meet unique power electronics requirements
The method employed using Simcenter POWERTESTER 1500A complies with the JEDEC JESD51-14 standard. demonstrating a non-invasive electrical test to both heat the die and detect the die temperature.
JEDEC is the industry leader for creating open standards for the microelectronics sector. Accredited by ANSI, this regulatory body ensures product compatibility, improves time-to-market and lowers product development costs for the benefit of the industry and, eventually, the consumer.
What you will learn in this die attach thermal performance paper
Follow along as ON Semiconductor:
Explains how the thermal performance of the package is affected by the size, location, and distribution of voids
Determines the most accurate method and tools for calculating the junction-to-case resistance
Analyzes the implications of die attach layer voids on the junction-to-case resistance
Measures ten samples, a through j, using the temperature versus time derivative method
Want to learn more? Download and read the whitepaper.