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White Paper

Formally Ensuring Equivalence Between C++ and RTL Designs

Moving untimed C++ design descriptions through a High-Level Synthesis (HLS) flow, designers wonder if the generated timed RTL is functionally equivalent to the original, high-level description. When they make refinements or optimize RTL for power, they naturally are concerned that these changes no longer meet their original specifications. They could create testbenches and run verification at every step of the flow, but that takes too much time and can wreck a production schedule. What designers really need is a way to quickly determine design equivalence without the need for testbenches and simulation runs. That is where formal, sequential logic equivalent checking, SLECĀ® HLS comes to the rescue. In this whitepaper, learn why SLEC HLS is a vital piece of the CatapultĀ® verification flow, how it works, and why the tool is unique in the marketplace.