SLEC System Factsheet

SLEC System is a good fit for design teams verifying their RTL implementation by formally comparing it against functional SystemC/C++ models, as it significantly reduces the time and effort to establish confidence that the intended functionality is maintained.

The system models can be leveraged completely for verifying the RTL blocks without the need for testbenches and tests by using a Tcl setup, making the tool intuitive and easy to use. This approach is helpful both where design flows involve C-level descriptions and where exorbitantly large state spaces make simulation-based verification approaches impractical.