Effective identification of reset tree bugs to mitigate RDC issues

In today’s landscape of growing design complexity, the reset architecture of a SoC design can be very complicated. Designs have multiple reset sources, leading to a reset tree that is larger and more complex than the clock tree. The challenges and considerations traditionally associated with clock tree synthesis are now equally relevant to reset tree synthesis. The errors in a reset tree can lead to metastability, glitches or other functional failures of the system. Such errors are generally not caught by linter tools and need a dedicated solution to verify the reset tree structure.

Reset tree structure verification aids the designer to identify design issues early before reset domain crossing (RDC) analysis, thereby, saving time and effort. RDC static verification tools offer a set of basic structural checks that help designers ensure the accuracy of the reset tree structure. However, to further reduce the risk of costly silicon re-spins, more sophisticated checks are necessary for the reset trees. This paper discusses these advanced structural checks, explaining how they are crucial for identifying potential issues early and ensuring the integrity of SoC designs.

By incorporating more advanced structural checks that go beyond basic reset tree validation techniques, designers can significantly improve the reliability of their SoC designs, ensuring that reset domain crossings are handled properly and avoiding critical errors that could impact the functionality and stability of the system.