Shared bus interfaces and memory test
These days, designs contain a huge number of memory arrays embedded in the core, and these memories often consume a substantial portion of the total chip area. This increase in memory size and number implies extra hardware cost for the associated memory built-in self-test (MBIST) logic. In addition to the area of the MBIST logic, there may be additional costs due to increased routing. It may even negatively impact the chip's performance in the critical functional paths to and from memories. A shared bus architecture provides a common access point for several memories, allowing users to optimize routing and core performance. In addition, a shared bus architecture provides flexibility to users to route design-for-test (DFT) signals along functional paths behind the shared bus interface. Tessent MemoryBIST instruments automatically connect to the DFT signals to apply MBIST patterns through the shared bus interface.