Assuring the integrity of RISC-V cores and SoCs
GapFree Verification Process
This paper presents the Siemens EDA RISC-V Integrity Verification solution and discussed how its components verify all four aspects of design integrity at both the processor core and full- chip levels. It concludes by detailing some issues found by the Siemens EDA solution on RISC-V core and SoC designs available as open source.
Like previous generations of reduced instruction set computer (RISC) designs, RISC-V has its roots in academia. The project to develop a fifth-generation RISC- based instruction set architecture (ISA) began in 2010 in the EECS Department at the University of California at Berkeley. As with previous RISC projects both academic and commercial, the goal was to define an ISA enabling small, fast designs with the potential for low-power operation when needed. Unlike some of those other projects, the intent was for RISC-V to support a wide variety of diverse implementations. This required the ISA to have the flexibility to map to many different microarchitectures with different power, performance, and area (PPA) tradeoffs appropriate for targeted end applications.
In 2015, the RISC-V Foundation was established to own, maintain, and publish the ISA and related documents. The original RISC-V authors and developers surrendered their rights to the foundation. There are now nearly 250 members, spanning universities, semiconductor suppliers, system houses, software vendors, and IP providers. The Foundation ensures that RISC-V remains open as per the original vision of its developers. This openness is a sharp contrast to the proprietary ISAs that have dominated computing for decades and has at least three dimensions. First, the RISC-V ISA has been developed and evolved by a wide circle of collaborators from both industry and academia. Anyone can contribute ideas and participate in the discussions, although the ability to vote is reserved for members of the Foundation, which anyone can join.