ST: Using Calibre DesignEnhancer Via to improve design quality and reduce support cost

Power management in integrated circuit (IC) designs is a growing challenge for both design companies and foundries. integrated circuit power issues are impacted by multiple causes; accordingly, a complete power optimization resolution requires multiple methodologies throughout the design flow. Power grid challenges are mainly voltage drop (IR) and electromigration (EM) issues that are growing in number and impact. Lowering metal resistance is one of the ways for designers to get reliable, robust designs. When the layout is edited to lower resistance it is critical that the modifications are done with a complete understanding of the DRC rules to reduce design iterations. Analysis based automated layout optimization during design stages helps designers to deliver “DRC-clean” designs to tape out faster while improving design manufacturability and circuit reliability. Calibre DesignEnhancer provides not only “DRC-clean” results but uses the Calibre platform to maximize the insertion rate. In this presentation we will also show how DesignEnhancer makes it easy to maintain, integrate with various design tools and move to multiple technologies. These factors have enabled ST to reduce product design cycle time and the work cost.