Semiconductor design: Linking design to manufacturing for a sustainable semiconductor future
EE Times - Fireside chat with Michael Munsey, VP, Siemens EDA
Semiconductor sustainability starts with design and the decisions made during the design process affect sustainability. This is amplified as we transition to the heterogeneous integration of chiplets using advanced substrate platforms such as 2.5/3D in order to continue silicon scaling. By linking the digital twins for semiconductor design to the digital twin of a semiconductor fab, design details can be fed forward to optimize fabs for sustainability and manufacturing data can be fed back to optimize design libraries and decisions.
In this fireside chat session, EE Times' Sally Ward-Foxton chats with Siemens EDAs Michael Munsey about the evolution of the digital twin, how new solutions aid design and manufacturability, and the start of a new semiconductor era.
Related resources
SLEC System Factsheet
SLEC System is a good fit for design teams verifying their RTL implementation by formally comparing it against functional SystemC/C++ models
Catapult High-Level Synthesis and Verification Fact Sheet
Industry leading C++/SystemC High-Level Synthesis with Low-Power estimation/optimization. Design checking, code and functional coverage verification plus formal make HLS more than mere “C to RTL.
StreamTV’s SeeCubic: Catapult HLS enables Ultra-D 3D without glasses
StreamTV's SeeCubic faced an impossible task: develop a real-time conversion IP block for a custom SoC without knowing the target technology. This IP was critical for their glasses-free 3D solution.