Leveraging the RISC-V Efficient Trace (E-Trace) Standard
Processor trace gives developers access to critical insights and forensic capabilities to manage the risk of building embedded systems. Siemens, a lead technical contributor to the RISC-V Efficient trace (E-Trace) specification, will in this presentation cover an overview of the trace specification and discuss how processor trace is used to improve embedded software and applications and what is contained in the trace specification.
Related resources
Tessent Secure Message Infrastructure
The Secure Message Infrastructure provides the communication fabric to any Tessent Embedded Analytics system, allowing SoC designers to create system-wide analysis, optimization and security implementations.
Tessent UltraSight-V – An on-chip debug and trace solution for RISC-V systems
Siemens is a key contributor to the RISC-V Efficient trace (E-trace) specification. This presentation will include a demonstration of the UltraSight-V solution.
Tessent Embedded Analytics product guide
Tessent Embedded Analytics provides semiconductor intellectual property (SIP) that allows designers to monitor and analyze systems-on-chip (SoCs).