Taking 2.5D/3D IC physical verification to the next level

As package designs evolve, so do verification requirements and challenges. Designers working on multi-die, multi-chiplet stacked configurations in 2.5/3D IC designs can use Calibre 3DStack physical verification checks to verify die alignments for proper connectivity and electrical behavior. The Calibre 3DStack precheck mode enables design teams to find and correct basic implementation mistakes and systemic errors before invoking the Calibre 3DStack signoff run, eliminating unnecessary debugging iterations and speeding up the overall package verification flow.

The Calibre 3DStack tool helps make 2.5D and 3D IC physical verification faster, more accurate, and easy to use

Siemens EDA support for 2.5/3D IC verification has grown right along with the use of multi-die, multi-chiplet stacked configurations. We enhanced Calibre 3DStack checks to ensure more accurate alignment checking between die, and added a precheck mode that enables engineers to catch multiple setup/data issues before invoking signoff runs. Finding and correcting basic implementation mistakes and systemic errors before invoking the Calibre 3DStack signoff run eliminates unnecessary debugging iterations and speeds up the overall package verification flow.

In addition, Calibre 3DStack integration with the Xpedition Package Designer and Substrate Integrator tools helps speed implementation, while ties to industry-leading parasitic extraction tools enable capture of coupling across die or package interfaces. Extending other traditional IC verification tools, such as reliability verification, to recognize and address package issues empowers design companies to further enhance the market value of their high-density advanced packaging products.