Model-based CAOPC flow for memory chips to improve performance and consistency of RET solutions

Maximizing yield for memory devices requires that resolution enhancement techniques (RET) produce perfect geometric consistency without compromising the lithographic quality. This work adopts an approach that leverages the inherent repetitive and hierarchical structure of the cell-array to ensure the lithographic quality and perfect geometric consistency and symmetry in addition to a drastic reduction in runtime and mask tapeout turn-around-time. A version of this paper was originally presented at SPIE 2020 and published in the proceedings.