Machine learning-powered etch bias prediction for etch retargeting flow enhancement

This paper presents a novel approach to predict etch bias using machine learning (ML) techniques, which can replace the traditional rule-based etch bias tables. The proposed ML-based method offers significant advantages in terms of faster turnaround time and operational simplicity compared to the conventional approach.

The ML-based flow involves three main steps: feature vector collection, ML model training and prediction. The trained ML model achieves good performance metrics and demonstrates 100% compliance with the specified error limits for both 1D and 2D patterns. Validation of the ML-predicted etch bias shows that the prediction errors are predominantly within 0.5 nm for symmetric patterns, translating to approximately 0.25 nm etch bias error per side.

The paper also investigates the interpolation capability of the ML model using a synthetic through-pitch test case. Initial results show oscillations in the etch bias predictions, particularly for smaller feature CDs, due to insufficient coverage in the training data. By expanding the training data to include more representative patterns, the oscillations in the etch bias predictions can be significantly reduced, demonstrating the importance of comprehensive data coverage for effective ML model performance.

This paper was presented at the 2025 SPIE Advanced Lithography +Patterning symposium.

What you'll learn:

• How a machine learning-based approach to predict etch bias can replace traditional rule-based etch bias tables, providing faster turnaround time and operational simplicity.
• What is the process of developing the ML-based etch bias prediction flow, including feature vector collection, model training, and making accurate predictions that meet specified error limits.
• The importance of comprehensive training data coverage, especially for handling asymmetric patterns and enabling robust interpolation of etch bias across different feature CDs and pitches.

Who should read this:

• Mask synthesis engineers
• Semiconductor process engineers and researchers
• CAD managers