Guided random synthetic layout generation and machine-learning based defect prediction for leading edge technology node development

This paper presents a novel approach that combines guided synthetic layout generation and machine learning (ML)-based defect prediction to accelerate the development of new semiconductor technology nodes. The method addresses challenges faced in the early process development phase when design rules are not fully established and real product designs are limited.

The proposed flow starts with generating guided synthetic layouts that stress minimum design rule constraints, complementing existing functional and OPC macros. These synthetic patterns are then used to efficiently identify process hotspots through SEM inspection, improving defect inspection efficiency. The silicon results are leveraged to calibrate an ML-based defect prediction model.

The ML model can perform defect-specific predictions at both the fragment level and full-chip level, enabling targeted metrology data collection in anticipated hotspot areas. The approach demonstrates strong performance, achieving ROC AUC scores of 0.83 and 0.70 for detecting M1 pinching and line-end pullback defects, respectively, while maintaining high precision.

The combination of guided synthetic layout generation and ML-based defect prediction represents a significant step forward in incorporating intelligent automation into advanced semiconductor development. This methodology has the potential to reduce development costs and accelerate time to market for new technology nodes by enabling early-stage defect identification and process optimization.

This paper was presented at the 2025 SPIE Advanced Lithography + Patterning symposium.

What you'll learn:

• How to use guided synthetic layout generation to create high-quality test patterns that complement existing designs and enable early exploration of critical design spaces.
• The process of developing and calibrating machine learning-based defect prediction models to achieve high accuracy in detecting specific defect modes, such as M1 pinching and line-end pullback.
• The benefits of integrating synthetic layouts and ML-based hotspot detection to enable targeted inspection strategies, improving the efficiency of metrology resource allocation during advanced semiconductor development.

Who should read this:

• Semiconductor process engineers and R&D teams involved in the development of advanced technology nodes, particularly those working on patterning, yield enhancement and defect detection.
• Engineering managers and decision-makers in semiconductor fabs and design houses who are looking to accelerate the development cycle and improve the efficiency of their processes for new technology introductions.
• Researchers and experts in the field of machine learning applications for semiconductor manufacturing, who are interested in exploring the integration of synthetic data generation and ML-based predictive models.