Automated waiver management for IC reliability verification

Not every error found during reliability verification requires debugging and correction. Error waivers can be an important part of an efficient reliability verification flow, but they must be applied and processed accurately to ensure the integrity of the design is maintained. The Calibre® PERC™ advanced automated waivers functionality supports a full range of waivers needs, including automated waiver processing, the ability to waive combined topological and geometrical violations, and a controlled methodology for multi-user environments.

Automated error waiver management enhances IC design reliability verification

Calibre PERC automated waiver processing supports both IP and full-chip waivers management in IC design reliability verification The unique technology enables accurate processing of waivers that combine topological and geometrical information. Not only can waivers be automatically generated, but a controlled process flow supports multi-user waiving while ensuring design integrity.