SLEC System Factsheet
Siemens Digital Industries Software High-Level Verification
SLEC System is a good fit for design teams verifying their RTL implementation by formally comparing it against functional SystemC/C++ models, as it significantly reduces the time and effort to establish confidence that the intended functionality is maintained.
The system models can be leveraged completely for verifying the RTL blocks without the need for testbenches and tests by using a Tcl setup, making the tool intuitive and easy to use. This approach is helpful both where design flows involve C-level descriptions and where exorbitantly large state spaces make simulation-based verification approaches impractical.
Related resources
LG Electronics: Video Encoder IP Design Optimization and Verification Using Catapult
In this session, LGE describes a new design approach which concluded that adopting Catapult in IP development increases efficiency in time and cost, and they plan to increase usage in future IP projects.
Google develops WebM video decompression hardware IP using High-Level Synthesis
This paper will describe the actual use of Catapult High-Level Synthesis (HLS) by the WebM team in the successful implementation of the G2 VP9 and share results and impressions.
Chips&Media: Design and Verification of Deep Learning Object Detection IP
Chips&Media decided to adopt a new High-Level Synthesis flow to implement their deep learning algorithm. Enabling them now focus on algorithm and architecture design and reduce painful debugging and expensive computing resources.