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fact sheet

Questa Clock-Domain Crossing (CDC) verification

Siemens EDA automated CDC verification

Using only your RTL (and SDC constraints or UPF power intent files), Questa CDC solutions automatically generate and analyze assertions to guard against chip-killing CDC issues.
Using only your RTL (and SDC constraints or UPF power intent files), Questa CDC solutions automatically generate and analyze assertions to guard against chip-killing clock-domain crossing (CDC) issues.

The high risk of multiple clock domains

Designers increasingly use advanced multi-clock architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has more than one clock domain does not accurately model the silicon behavior related to the transfer of data between asynchronous clock domains. As a consequence, simulation does not accurately predict silicon functionality, risking show-stopper bug escapes.

Automated, exhaustive CDC verification

Questa® CDC identifies errors using structural analysis to recognize clock domains, synchronizers, and low power structures via the Unified Power Format (UPF). It generates assertions for protocol verification along with metastability models for reconvergence verification. All properties and design intent are inferred by the software.

The technology exhaustively checks all potential CDC failures, statically verifying that all signals crossing asynchronous clock domain boundaries are guarded by CDC synchronizers. It then illustrates DUT issues found with familiar schematic and waveform displays. Additionally, in concert with Questa simulation, the CDC-FX app injects metastability into RTL functional simulation to verify the DUT is tolerant of random delays caused by metastability.

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