Catapult High-Level Synthesis and Verification Fact Sheet
Design Platform Empowering Designers
Catapult High-Level Synthesis (HLS) has been proven in production design flows with 1,000s of designs and the resulting RTL adheres to the strictest corporate design guidelines and ECO flows. In addition to Catapult HLS, only Catapult has integrated High-Level Verification tools and methodologies that enable designers to complete their verification signoff at the C++ level with fast closure for RTL. Discover this industry leading family of products.
Catapult HLS Productivity Gain
To achieve the maximum productivity gain from a C++/SystemC HLS methodology, it is necessary to have the performance and capacity to handle today’s large designs coupled with a comprehensive flow through verification and implementation.
Related resources
Infineon & Coseda: Facelifting a SystemC System Level Model Towards Physical Prototype – Adoption of High-Level-Synthesis
Infineon & Coseda present on the adoption of High-Level-Synthesis at an existing SystemC system level model.
Infineon: HLS Formal Verification Flow Using Siemens Formal Verification
High-Level Synthesis (HLS) is design flow in which design intent is described at a higher level of abstraction such as SystemC/C++/Matlab/etc.
STMicroelectronics: A Common C++ and UVM Verification Flow of High-Level IP
STMicro presents a unified way to integrate the definition of RTL and C functional coverage and assertion (reducing the coding effort) and a method to add constraints to the random values generated in UVMF.
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Alibaba: Innovating Agile Hardware Development with Catapult HLS
At the IP level, an ISP was created within a year using Catapult, a task impossible using traditional RTL. To reduce dependency on designer experience, Alibaba introduced an AI-assisted DSE tool.