Catapult High-Level Synthesis and Verification Fact Sheet
Design Platform Empowering Designers
Catapult High-Level Synthesis (HLS) has been proven in production design flows with 1,000s of designs and the resulting RTL adheres to the strictest corporate design guidelines and ECO flows. In addition to Catapult HLS, only Catapult has integrated High-Level Verification tools and methodologies that enable designers to complete their verification signoff at the C++ level with fast closure for RTL. Discover this industry leading family of products.
Catapult HLS Productivity Gain
To achieve the maximum productivity gain from a C++/SystemC HLS methodology, it is necessary to have the performance and capacity to handle today’s large designs coupled with a comprehensive flow through verification and implementation.
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Catapult High-Level Synthesis and Verification Fact Sheet
Industry leading C++/SystemC High-Level Synthesis with Low-Power estimation/optimization. Design checking, code and functional coverage verification plus formal make HLS more than mere “C to RTL.
PowerPro Low-Power
The PowerPro Platform provides a complete solution to accurately measure, interactively explore and thoroughly optimize power during the RTL development cycle. Using PowerPro, designers achieve maximum power reduction for SoC.