Shift left with Calibre to optimize IC design flow productivity, design quality, and time to market
Every IC designer strives to create a “clean,” or error-free, cell, block, chiplet, SoC, or 3D IC assembly before passing their work downstream for full signoff verification. However, waiting until signoff verification to find out how well you did is probably the least efficient approach to achieving production-ready layouts, impacting engineer productivity, project schedules, and hardware resources.
The shift left benefits in IC design verification
A shift left approach to IC design in which verification analysis is performed early and throughout the IC design cycle delivers significant competitive advantages. Early analysis capabilities available in the Calibre® nmPlatform toolsuite provide proven, innovative shift left solutions, including artificial intelligence, that allow design companies to achieve the productivity, efficiency, and cost reductions they are seeking while ensuring Calibre-quality results.
Download our technical paper to learn more.
Související zdroje informací
Xperi®: A Designer’s Life with HLS
This webinar will discuss two aspects of their experience going from RTL to HLS. The first topic is using HLS for algorithms such as Face Detection th
High-Level Synthesis Verification Technologies and Techniques
This session will describe applying known and trusted static, formal and dynamic approaches to verification performed at the C++ or SystemC HLS level of abstraction.
NVIDIA: High-Level Synthesis in Agile System-on-Chip Flows: Overview and Techniques
This talk provides a brief overview of NVIDIA Research’s use of Catapult HLS and highlights some useful features and flows of the Connections library, such as the ability to back-annotate SystemC simulations.