Samsung: Clock domain crossing aware sequential clock gating
Success story
Sequential clock gating optimizations
The sequential clock gating optimizations can use signals from across sequential boundaries and thus, can introduce new clock domain crossing (CDC) violations which can cause catastrophic functional issues in the fabricated chip. Hence, it has become very important that sequential clock gating optimizations be CDC aware.
In this paper, we present an algorithm to handle CDC violations as part of the objective function for sequential clock gating optimizations. With the proposed algorithm, we have obtained an average of 22% sequential power savings – this is within 3% of the power savings obtained by the CDC unaware sequential clock gating. In comparison, the state-of-the-art two-pass solution is leading to an almost complete loss of power savings.