New innovative way to functionally verify heterogeneous 2D/3D package connectivity

Functional verification of multi-chiplet packages connectivity

The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high performance compute segemnts such as AI, Hyperscalers, Cloud datacenters, Neural processors and even autonomous vehicles. With the quantity of chiplets commonly exceeding double-digit numbers. Add to that the increasing usage of high-speed, low power and low latency high-bandwidth-memory (HBM_) stacks the resultant designs often exceed 1M+ total pins. With that many device pins the resultant connectivity is massive making the task of verifying the connectivity’s correctness exceptionally challenging and time consuming. The traditional way to verify the connections requires a lot of manpower and time and is either not exhaustive or too late in the process. In this paper we introduce a new way to verify the package connectivity using formal verification that can exhaustively verify all interconnections between the chiplet blocks. The flow is automatic for all steps from creating the connectivity specification to verifying the package assemblies output connectivity. The automatic parallel algorithms execute on a compute grid and verify huge numbers of connections in minutes even seconds.