How Siemens Symphony Pro enabled AnalogPort to verify complex chip interfaces

The semiconductor industry's shift toward chiplet-based architectures has created significant mixed-signal verification challenges for high-speed die-to-die interconnects. Traditional verification approaches force difficult trade-offs: Digital mixed-signal (DMS) flows sacrifice analog fidelity, while Analog mixed-signal (AMS) flows struggle with scalability and manual overhead. This paper details how AnalogPort, a leading high-speed interconnect solutions provider, successfully addressed these limitations using Siemens EDA's Symphony Pro (part of SolidoTM Simulation Suite) for their complex 32 Gbps, 16-transmit/16-receive full-duplex interface. Symphony Pro enabled AnalogPort to deploy UVM methodology while seamlessly combining high-fidelity SPICE simulation for critical analog blocks with high-performance digital simulation for the broader system. By extending their UVM-based digital verification into the mixed-signal domain, AnalogPort achieved a standardized, scalable flow that delivered both analog accuracy and simulation performance, successfully meeting strict project timelines.