白皮書

Catapult LP 提供功耗最佳化 ESL 硬體實現流程

Catapult LP 提供功耗最佳化 ESL 硬體實現流程

本白皮書大致說明了用於探索低功耗架構的 Catapult 流程，並詳細探討了使用 Catapult LP 設計流程可以實現的低功耗最佳化成果。本次案例研究是使用真實的客戶設計。Catapult 分別在啟動和未啟動低功耗最佳化的情況下合成這些設計。在啟動低功耗最佳化的情況下，Catapult 在背景中使用 Calypto 的 PowerPro 技術來進行 RTL 功耗最佳化和估算功耗的使用情形。

Share

相關資訊

Transforming semiconductor manufacturing through digital innovation
Webinar

Transforming semiconductor manufacturing through digital innovation

Watch our on-demand webinar to learn how smart manufacturing for semiconductors digital thread technology creates virtual manufacturing representations, enables real-time analytics and improves collaboration.

From chaos to collaboration: synchronizing ECAD and MCAD design domains
Webinar

From chaos to collaboration: synchronizing ECAD and MCAD design domains

Learn how to improve collaboration between ECAD and MCAD teams to reduce errors, minimize rework and accelerate development of complex electronic products.