Beyond UVM registers - better, faster, smarter
The UVM Register package is a large part of the UVM.
Adoption of SystemVerilog UVM is growing stronger. Verification teams are expanding their knowledge with respect to UVM features and capabilities. These verification teams are using the UVM Register layer with good success. But the UVM Register layer has many moving parts and intricate details. It can be difficult to adopt and it can be difficult to model complex registers. It is a complex system.
In this paper we review the concepts behind the UVM Register package and try to think about creating a different kind of register model, one that achieves the same goals with much less detail and much less moving parts.
The UVM Register package[2] has many features. These features include reading and writing register values, reading and writing register fields and register blocks. The register model keeps track of the expected value and can directly access the actual modeled register using “back-door access”. Using the register model allows a testbench to be written that can check the behavior of registers and address maps. Additionally, the register model can be constrained and randomized to provide stimulus or configurations. It can also be “covered” with functional coverage. These are the main operations of any register package; model the expected and actual values; check address mapping; generate random stimulus; allow direct access; support functional coverage.
The problem in the UVM Register package arises in the intricacies in the register layer source code. For uvm- 1.1d, there are 26 files containing over 22,000 lines of source code. That represents 19 percent of the total number of files in the UVM, and 32 percent of the total number of lines of source code. Clearly the UVM Register package is a large part of the UVM. In the next release, uvm-1.2, the percentages are reduced by increasing the files and lines in the overall UVM, but the absolute number of files is still 26, and the lines of source code is still over 22,000 for the UVM Register package. In the uvm1.1d User Guide, the description of the UVM Register layer is 26 percent of the number of pages.