A novel simulation flow for DDR5 systems with clocked receivers

DDR5 is the latest generation of SDRAM technology, with data transfer rates eventually reaching up to 8800MT/s. To help recover timing and voltage margin at the receiver, the DDR5 specification requires the DRAM include a decision feedback equalizer (DFE). Traditionally, the electrical performance of the input signals to the DRAM is evaluated at the pins of the device. However, the DFE’s equalization isn’t visible at the DRAM pins and thus for DDR5 the evaluation point is shifted to the output of the DFE inside the DRAM die. But because the DQS provides the DFE clock input, the DFE output is affected by the combination of data and strobe signal integrity.

In this paper

This paper begins with an overview of the DDR5 specification, forwarded-clock architectures, and equalization techniques. The unique aspects of DDR5 IBIS-AMI models and the resulting impacts to the simulation methodology are explored. A novel EDA tool simulation flow for capturing both the non-LTI effects in the DDR5 system and the low BER required in the DDR5 specification is presented. Clocked IBIS-AMI receiver models are then introduced into the simulation flow, and the resulting impact to jitter and crosstalk are presented. Finally, future challenges for simulating DDR5 systems are discussed.

Contents

• Introduction
• DDR5 JEDEC specification from a simulation
  perspective
• DDR5 device models
• Novel clocked simulation flow
• A custom advanced IBIS-AMI flow
  Conclusion