Preparation and performance review using Calibre PERC reliability ESD to prepare for chiplet area

Tool performance and runtime optimization to obtain job’s result with best use of cloud compute resource is a challenging topic, especially for reliability check as the time window to run these checks & annalyse results between LVS clean and TapeOut is quite reduced.

In addition, the recent trend about chiplet and new advance packaging technics, predicted by Gordon Moore in 1965, are multiplying the number of interface (>20000K IOs). Each interface of a chiplet need to be verified against ESD events and force ESD experts to run job using a lot of memory and compute resource. We will discuss how Intel, in collaboration with SEDA Application Engineer, starts to monitor and improve systematically compute time efficiency for complex ""Calibre PERC"" runs.